Reverse engineered a circuit board

[Bruce Griffing]

I buy that....also did a quick search on ebay, the CNC add on memory boards do not seem to be that expensive, or at least i did not run into any that is.

dee
;-D

True, but you will not find any options whatsoever for some controls.

 

[dcsipo]

True, but you will not find any options whatsoever for some controls.

any candidates? and what would be a fair price for them. Just because the part is unobtanium it does not mean it can be way overpriced. At one point no one will buy it....

dee
;-D

 

[laggeddag]

Ive found a much more streamlined process now to go from the PCB image to vectors, including this step which allows removal of unused pads and a verification image to quickly confirm nothing important was zapped

It only took 6 minutes to prepare the PCB for scanning and the image enhancement another 5 minutes or so. Vectorisation happens pretty much instantly after that and then the DXF can be imported into PCB cad software.

 

[Perry Harrington]

I know for a fact that Fadal memory boards are single source at this point. The problem is that for the popular control revisions, they have PALs and CPLDs on them for address management.

I think the manufacturer has some OE proprietary fuse maps for these devices, because it's VERY doubtful that they reverse engineered the fuse maps or read them out.

 

[dcsipo]

I know for a fact that Fadal memory boards are single source at this point. The problem is that for the popular control revisions, they have PALs and CPLDs on them for address management.

I think the manufacturer has some OE proprietary fuse maps for these devices, because it's VERY doubtful that they reverse engineered the fuse maps or read them out.

You mean the address bus is not a straight address bus? Or you mean the address management once you are on the board? There you need to manage the individual chip addressing. Say if the bus is a simple 16 or more address lines then the address management on the board is chip specific, nowadays just pick a chip that you can hook up directly to the bus and use some drivers that supply the required current a voltages. Some of these things may actually run on buses like VME or VERSA or even EISA or some other flavor of 80s 90s computer bus. Drivers available for those from many sources. I know we played the same trick in telco equipment designs, used a standard bus but added secondary controls and junk so it was not recognizable any more but it was still a standard computer bus in there. The boards were a different form factor and the connectors were custom.


dee
;-D

 

[Perry Harrington]

The later Fadal memory cards have barely enough I/O for the data lines and the address bus.

They have upgrades that use 512KB chips and have to do all the addressing of those individual chips to turn it into a linear memory bank.

The -4 boards were based on a 286, while the -5 are 386sx, the -6 boards are 486 chips, from what I've been able to suss out from ebay auctions.

The 286 and 386sx have 24 address lines and 16 data lines, plus some enable logic. The 486 has a 32bit address space and 32bit data bus.

For 16MB you need 24 address bits and 16 data bits, but the individual chips only have 19 address bits and 8 data bits, so you have to gang them up in pairs for 16bit data width and handle address decoding.

I'm guessing the CPLD was used primarily for address decoding, but Fadal may have been pinching pennies in their designs, leading to even more funky stuff.

Fadal memory mapped the video ram into processor space, using a dual ported ram, so that eats away at the 16MB limit. Many of the peripherals were memory mapped in Fadal controls, leading to more address space waste.

What's funny is that they claim the minimum RAM is 38KB, which is 32KB of actual system RAM, 1KB of video RAM, and 1KB of RAM for each axis card. Only the main 32KB was used for program storage and execution, the other ram was for display and scratch pad ram on the axis cards.